Are you a Systems Engineer? Are you sick and tired of hearing about Verification and Validation (V&V) that you would puke the next time you hear it? Then stop reading this because I am just going to repeat what you’ve probably known.<\/p>\n\n\n\n
The axioms are Validation is doing the right thing while Verification is doing the thing right. I find this confusing as English is not my mother tongue and the tongue twister of putting the word ‘right’ at the right place is, confusing. Another way is that people say Validation is only at the start and Verification is throughout the project, which I think is true, as V&V report is normally done at phase 1 and phase 7, or the last phase, as per BS EN 5012X (or other IEC 61508 derivatives) but what happens if the phase is more than 7 phases? Or less. Easy some people might say, verification just happens along the V while validation happens ‘across’ the V. Yeah I’ve used this explanation too but it’s not very clear.<\/p>\n\n\n\n
I’ve come up with this analogy, where let’s say you are a baker. A customer asks for a cake, which you then bake according to a recipe. When you check whether you are following the recipe, that is verification. Recipe = Verification. Verecipefication. Voila!<\/p>\n\n\n\n
Then you give the cake to the customer. After he\/she ate the cake, then it is validATEd. Get it? <\/p>\n\n\n\n
The end. Now I’ll stop talking about V&V.<\/p>\n\n\n\n
Thank you for reading.<\/p>\n","protected":false},"excerpt":{"rendered":"
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